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• 721b1fb5c6
  Testbenches main Yannick Reiß 2024-02-04 12:08:07 +0100
• a519e55f5b Add Cpu16 bitstraem = 2024-02-01 09:16:47 +0100
• 3bc4b6855e Add example PMem, Connect constraints = 2024-02-01 09:11:45 +0100
• fd8b4f9f85 Add constraints = 2024-02-01 09:11:13 +0100
• 3e8a72fa05 Add unconditional jump expressions = 2024-02-01 08:01:24 +0100
• d27dee2745 Jump only if branch acknowledges = 2024-02-01 07:49:29 +0100
• 8c4286cd90 Always using 32 bit instructions, Implement enable handler = 2024-02-01 07:47:21 +0100
• d57ca49821 Implement and connect branch = 2024-02-01 06:58:12 +0100
• 8f14afc6ec Removed Bus access from RAM = 2024-01-31 17:39:33 +0100
• fafd9320af
  Connecting I2C Yannick Reiß 2024-01-31 15:20:17 +0100
• 4385bc6dcc
  Forgot signal keywords Yannick Reiß 2024-01-31 14:54:08 +0100
• 18010b4821
  Implement clock splitter for I2C Yannick Reiß 2024-01-31 14:52:46 +0100
• f8076f66cb
  Fix loop assignment Yannick Reiß 2024-01-31 13:18:15 +0100
• 34bc6162ed
  Not driving multiple ports now Yannick Reiß 2024-01-31 13:16:09 +0100
• c1ddd00634
  Add I2C Entity Yannick Reiß 2024-01-31 13:12:34 +0100
• c5853fc280
  Add I2C to RAM Yannick Reiß 2024-01-31 12:47:15 +0100
• 9505af3467
  RISCV V1 Yannick Reiß 2024-01-30 21:50:57 +0100
• 683ac9a8d4
  init Yannick Reiß 2024-01-30 09:42:06 +0100