Update Verilog snippets

2023-08-26 08:21:47 +02:00
parent a4bd9d253b
commit 583d6f9790
5 changed files with 15 additions and 0 deletions
--- a/spell/de.utf-8.add
+++ b/spell/de.utf-8.add
@@ -0,0 +1,2 @@
+transgender
+python
--- a/spell/de.utf-8.add.spl
+++ b/spell/de.utf-8.add.spl
--- a/spell/en.utf-8.add
+++ b/spell/en.utf-8.add
@@ -0,0 +1 @@
+t0
--- a/spell/en.utf-8.add.spl
+++ b/spell/en.utf-8.add.spl