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26 Commits 3 Branches 0 Tags 455 KiB
Vim Snippet 63.1%
Lua 36%
Vim Script 0.9%
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Yannick Reiß 706051c4e0
Add Verilog snippet 		2023-08-27 16:46:52 +02:00
UltiSnips Add Verilog snippet 2023-08-27 16:46:52 +02:00
lua update 2023-08-22 07:46:14 +02:00
python init 2023-07-31 17:35:26 +02:00
viml update 2023-08-22 07:46:14 +02:00
.gitignore gitignore 2023-07-31 18:16:40 +02:00
init.lua update 2023-08-22 07:46:14 +02:00
lastSession.vi update 2023-08-22 07:46:14 +02:00
legacyconf.log update 2023-08-22 07:46:14 +02:00