Stack implementation (Faulty)

Makefile

@@ -1,7 +1,7 @@
 CHDL	=	ghdl
 FLAGS	=	--std=08
 STOP	=	60000ns
-PARTS	=	alu stack
+PARTS	=	alu
 
 all: $(PARTS)
 
@@ -15,4 +15,4 @@ clean:
 	find . -name '*.cf' -exec rm -r {} \;
 	find . -name '*.ghw' -exec rm -r {} \;
 	find . -name '*.entity' -exec rm -r {} \;
-	find . -name '*_tb' -exec rm -r {} \;
+	find . -name $(PARTS)_tb -exec rm -r {} \;

stack.vhd

@@ -0,0 +1,71 @@
+-- stack.vhd
+-- Date:   Mon Mar  4 09:40:36 2024
+-- Author:    Yannick Reiß
+-- E-Mail:    yannick.reiss@nickr.eu
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity stack is
+  port(
+    clk            : in  std_logic;     -- clk
+    enable         : in  std_logic;     -- on enable do op
+    op             : in  std_logic;     -- 0 = pop, 1 = push
+    data_store     : in  std_logic_vector(7 downto 0);  -- Byte to store
+    alert_overflow : out std_logic;  -- Signal when stack pointer is at limit
+    data_out       : out std_logic_vector(7 downto 0);  -- Byte from memory
+    block_parity   : out std_logic      -- parity over all bits
+    );
+end stack;
+
+architecture Mem of stack is
+  type memblock is array(0 to 63) of std_logic_vector(7 downto 0);
+
+  signal memory          : memblock                     := (others => (others => '0'));
+  signal stack_pointer   : std_logic_vector(5 downto 0) := (others => '0');
+  signal s_parity        : std_logic                    := '0';
+begin
+
+  mem_logic : process(all)
+  begin
+    if rising_edge(clk) then
+      if enable = '1' then
+
+        -- read or write memory
+        if op = '1' then
+          memory(to_integer(unsigned(stack_pointer))) <= data_store;
+        end if;
+
+        -- adjust stack pointer
+        if op = '1' then
+        -- stack_pointer <= std_logic_vector(unsigned(stack_pointer) + 1);
+        else
+        -- stack_pointer <= std_logic_vector(unsigned(stack_pointer) - 1);
+        end if;
+      end if;
+    end if;
+  end process mem_logic;
+
+  set_parity : process(memory, s_parity)
+  begin
+    for i in memory'range loop
+      for j in memory(i)'range loop
+        s_parity <= s_parity xor memory(i)(j);
+      end loop;
+    end loop;
+  end process set_parity;
+
+  set_limit : process(clk)
+  begin
+    if rising_edge(clk) then
+      if unsigned(stack_pointer) = 63 then
+        alert_overflow <= '1';
+      else
+        alert_overflow <= '0';
+      end if;
+    end if;
+  end process set_limit;
+
+  block_parity <= s_parity;
+  data_out     <= memory(to_integer(unsigned(stack_pointer) - 1));
+end Mem;

tb_alu.vhdl

@@ -59,7 +59,7 @@ begin
     target      <= operand1 xor "11111111";
     wait for 5 ns;
     if not (target = result) then
-      write(lineBuffer, string'("=> Error on Not"));
+      write(lineBuffer, string'("Error on Not"));
       writeline(output, lineBuffer);
     end if;
 
@@ -69,7 +69,7 @@ begin
     target   <= "00000000";
     wait for 5 ns;
     if not (unsigned(result) = unsigned(target)) then
-      write(lineBuffer, string'("=> Error on Parity"));
+      write(lineBuffer, string'("Error on Parity"));
       writeline(output, lineBuffer);
     end if;
 
@@ -79,7 +79,7 @@ begin
     target   <= "00000010";
     wait for 5 ns;
     if not (unsigned(result) = 1) then
-      write(lineBuffer, string'("=> Error on Count"));
+      write(lineBuffer, string'("Error on Count"));
       writeline(output, lineBuffer);
     end if;
 
@@ -89,7 +89,7 @@ begin
     target   <= operand1 and operand2;
     wait for 5 ns;
     if not (result = target) then
-      write(lineBuffer, string'("=> Error on And"));
+      write(lineBuffer, string'("Error on And"));
       writeline(output, lineBuffer);
     end if;
 
@@ -98,7 +98,7 @@ begin
     operator <= "010001";
     wait for 5 ns;
     if not (result = (operand1 or operand2)) then
-      write(lineBuffer, string'("=> Error on Or"));
+      write(lineBuffer, string'("Error on Or"));
       writeline(output, lineBuffer);
     end if;
 
@@ -107,7 +107,7 @@ begin
     operator <= "010101";
     wait for 5 ns;
     if not (result = (operand1 xor operand2)) then
-      write(lineBuffer, string'("=> Error on Xor"));
+      write(lineBuffer, string'("Error on Xor"));
       writeline(output, lineBuffer);
     end if;
 
@@ -116,7 +116,7 @@ begin
     operator <= "011001";
     wait for 5 ns;
     if not (result = operand2) then
-      write(lineBuffer, string'("=> Error on Move"));
+      write(lineBuffer, string'("Error on Move"));
       writeline(output, lineBuffer);
     end if;
 
@@ -125,7 +125,7 @@ begin
     operator <= "011101";
     wait for 5 ns;
     if not (result = std_logic_vector(to_stdlogicvector(to_bitvector(operand1) sll to_integer(unsigned(operand2))))) then
-      write(lineBuffer, string'("=> Error on Shift left"));
+      write(lineBuffer, string'("Error on Shift left"));
       writeline(output, lineBuffer);
     end if;
 
@@ -134,7 +134,7 @@ begin
     operator <= "100001";
     wait for 5 ns;
     if not (result = std_logic_vector(to_stdlogicvector(to_bitvector(operand1) srl to_integer(unsigned(operand2))))) then
-      write(lineBuffer, string'("=> Error on Shift right"));
+      write(lineBuffer, string'("Error on Shift right"));
       writeline(output, lineBuffer);
     end if;
 
@@ -143,7 +143,7 @@ begin
     operator <= "000010";
     wait for 5 ns;
     if not (result = std_logic_vector(unsigned(operand1) + unsigned(operand2))) then
-      write(lineBuffer, string'("=> Error on Add"));
+      write(lineBuffer, string'("Error on Add"));
       writeline(output, lineBuffer);
     end if;
 
@@ -152,7 +152,7 @@ begin
     operator <= "000110";
     wait for 5 ns;
     if not (result = std_logic_vector(signed(operand1) - signed(operand2))) then
-      write(lineBuffer, string'("=> Error on Sub"));
+      write(lineBuffer, string'("Error on Sub"));
       writeline(output, lineBuffer);
     end if;
 
@@ -161,7 +161,7 @@ begin
     operator <= "000011";
     wait for 5 ns;
     if not (result = "00000000") then
-      write(lineBuffer, string'("=> Error on Set if Equal"));
+      write(lineBuffer, string'("Error on Set if Equal"));
       writeline(output, lineBuffer);
     end if;
 
@@ -170,7 +170,7 @@ begin
     operator <= "000111";
     wait for 5 ns;
     if not (result = "00000001") then
-      write(lineBuffer, string'("=> Error on Set if Lower"));
+      write(lineBuffer, string'("Error on Set if Lower"));
       writeline(output, lineBuffer);
     end if;
 
@@ -179,7 +179,7 @@ begin
     operator <= "001011";
     wait for 5 ns;
     if not (result = "00000001") then
-      write(lineBuffer, string'("=> Error on Set if lower unsigned"));
+      write(lineBuffer, string'("Error on Set if lower unsigned"));
       writeline(output, lineBuffer);
     end if;
 

tb_stack.vhdl

@@ -0,0 +1,98 @@
+-- tb_stack.vhdl
+-- Date:   Mon Mar  4 10:07:49 2024
+-- Author:    Yannick Reiß
+-- E-Mail:    yannick.reiss@nickr.eu
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library std;
+use std.textio.all;
+
+library work;
+
+entity stack_tb is
+end stack_tb;
+
+architecture Testbench of stack_tb is
+
+  signal clk            : std_logic;
+  constant clk_period   : time                         := 10 ns;
+  signal enable         : std_logic                    := '0';
+  signal op             : std_logic                    := '0';
+  signal data_store     : std_logic_vector(7 downto 0) := "00110011";
+  signal alert_overflow : std_logic                    := '0';
+  signal data_out       : std_logic_vector(7 downto 0) := (others => '0');
+  signal block_parity   : std_logic                    := '0';
+begin
+
+  uut : entity work.stack(Mem)
+    port map (
+      clk            => clk,
+      enable         => enable,
+      op             => op,
+      data_store     => data_store,
+      alert_overflow => alert_overflow,
+      data_out       => data_out,
+      block_parity   => block_parity
+      );
+
+  clk_process : process
+  begin
+    clk <= '0';
+    wait for clk_period/2;
+    clk <= '1';
+    wait for clk_period/2;
+  end process;
+
+  testing : process
+    variable lineBuffer : line;
+  begin
+    wait until rising_edge(clk);
+    write(lineBuffer, string'("Starting the simulator"));
+    writeline(output, lineBuffer);
+
+    -- Try pushing something
+    data_store <= "00011101";
+    op         <= '1';
+    enable     <= '1';
+    wait for 5 ns;
+    enable     <= '0';
+
+    -- Push
+    wait for 5 ns;
+    data_store <= "00011110";
+    op         <= '1';
+    enable     <= '1';
+    wait for 5 ns;
+    enable     <= '0';
+
+    -- Push
+    wait for 5 ns;
+    data_store <= "10011110";
+    op         <= '1';
+    enable     <= '1';
+    wait for 5 ns;
+    enable     <= '0';
+
+    -- Pop
+    wait for 5 ns;
+    op     <= '0';
+    enable <= '1';
+    wait for 5 ns;
+    enable <= '0';
+
+    -- Pop
+    wait for 5 ns;
+    op     <= '0';
+    enable <= '1';
+    wait for 5 ns;
+    enable <= '0';
+
+    write(lineBuffer, string'("End of simulator"));
+    writeline(output, lineBuffer);
+
+    wait;
+  end process;
+
+end Testbench;