99 lines
2.2 KiB
VHDL
99 lines
2.2 KiB
VHDL
-- tb_stack.vhdl
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-- Date: Mon Mar 4 10:07:49 2024
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-- Author: Yannick Reiß
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-- E-Mail: yannick.reiss@nickr.eu
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library std;
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use std.textio.all;
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library work;
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entity stack_tb is
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end stack_tb;
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architecture Testbench of stack_tb is
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signal clk : std_logic;
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constant clk_period : time := 10 ns;
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signal enable : std_logic := '0';
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signal op : std_logic := '0';
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signal data_store : std_logic_vector(7 downto 0) := "00110011";
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signal alert_overflow : std_logic := '0';
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signal data_out : std_logic_vector(7 downto 0) := (others => '0');
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signal block_parity : std_logic := '0';
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begin
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uut : entity work.stack(Mem)
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port map (
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clk => clk,
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enable => enable,
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op => op,
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data_store => data_store,
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alert_overflow => alert_overflow,
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data_out => data_out,
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block_parity => block_parity
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);
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clk_process : process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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testing : process
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variable lineBuffer : line;
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begin
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wait until rising_edge(clk);
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write(lineBuffer, string'("Starting the simulator"));
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writeline(output, lineBuffer);
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-- Try pushing something
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data_store <= "00011101";
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op <= '1';
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enable <= '1';
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wait for 5 ns;
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enable <= '0';
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-- Push
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wait for 5 ns;
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data_store <= "00011110";
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op <= '1';
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enable <= '1';
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wait for 5 ns;
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enable <= '0';
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-- Push
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wait for 5 ns;
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data_store <= "10011110";
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op <= '1';
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enable <= '1';
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wait for 5 ns;
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enable <= '0';
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-- Pop
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wait for 5 ns;
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op <= '0';
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enable <= '1';
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wait for 5 ns;
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enable <= '0';
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-- Pop
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wait for 5 ns;
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op <= '0';
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enable <= '1';
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wait for 5 ns;
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enable <= '0';
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write(lineBuffer, string'("End of simulator"));
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writeline(output, lineBuffer);
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wait;
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end process;
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end Testbench;
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