72 lines
2.0 KiB
VHDL
72 lines
2.0 KiB
VHDL
-- stack.vhd
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-- Date: Mon Mar 4 09:40:36 2024
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-- Author: Yannick Reiß
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-- E-Mail: yannick.reiss@nickr.eu
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity stack is
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port(
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clk : in std_logic; -- clk
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enable : in std_logic; -- on enable do op
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op : in std_logic; -- 0 = pop, 1 = push
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data_store : in std_logic_vector(7 downto 0); -- Byte to store
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alert_overflow : out std_logic; -- Signal when stack pointer is at limit
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data_out : out std_logic_vector(7 downto 0); -- Byte from memory
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block_parity : out std_logic -- parity over all bits
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);
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end stack;
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architecture Mem of stack is
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type memblock is array(0 to 63) of std_logic_vector(7 downto 0);
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signal memory : memblock := (others => (others => '0'));
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signal stack_pointer : std_logic_vector(5 downto 0) := (others => '0');
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signal s_parity : std_logic := '0';
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begin
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mem_logic : process(all)
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begin
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if rising_edge(clk) then
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if enable = '1' then
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-- read or write memory
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if op = '1' then
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memory(to_integer(unsigned(stack_pointer))) <= data_store;
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end if;
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-- adjust stack pointer
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if op = '1' then
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-- stack_pointer <= std_logic_vector(unsigned(stack_pointer) + 1);
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else
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-- stack_pointer <= std_logic_vector(unsigned(stack_pointer) - 1);
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end if;
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end if;
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end if;
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end process mem_logic;
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set_parity : process(memory, s_parity)
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begin
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for i in memory'range loop
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for j in memory(i)'range loop
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s_parity <= s_parity xor memory(i)(j);
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end loop;
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end loop;
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end process set_parity;
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set_limit : process(clk)
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begin
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if rising_edge(clk) then
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if unsigned(stack_pointer) = 63 then
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alert_overflow <= '1';
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else
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alert_overflow <= '0';
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end if;
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end if;
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end process set_limit;
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block_parity <= s_parity;
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data_out <= memory(to_integer(unsigned(stack_pointer) - 1));
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end Mem;
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