42 lines
1.2 KiB
VHDL
42 lines
1.2 KiB
VHDL
-- regs.vhd
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-- Date: Mon Mar 4 16:49:33 2024
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-- Author: Yannick Reiß
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-- E-Mail: yannick.reiss@nickr.eu
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity regs is
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port map(
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clk : in std_logic;
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write_enable : in std_logic;
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value_write : in std_logic_vector(7 downto 0);
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register1 : in std_logic_vector(2 downto 0);
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register2 : in std_logic_vector(2 downto 0);
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value_r1 : out std_logic_vector(7 downto 0);
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value_r2 : out std_logic_vector(7 downto 0)
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);
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end regs;
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architecture Implementation of regs is
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type regbench is array(0 to 7) of std_logic_vector(7 downto 0);
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signal registerblock : regbench := (others => (others => '0'));
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begin
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-- react only on clock changes
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process (clk) -- runs only, when clk changed
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begin
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if rising_edge(clk) then
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-- check if write is enabled
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if to_integer(unsigned(write_enable)) = 1 then
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-- write data_in to wr_idx
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registerblock(to_integer(unsigned(register1))) <= value_write;
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end if;
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end if;
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end process;
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value_r1 <= registerblock(to_integer(unsigned(register1)));
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value_r2 <= registerblock(to_integer(unsigned(register2)));
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end Implementation;
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