50 lines
1.1 KiB
VHDL
50 lines
1.1 KiB
VHDL
-- tb_regs.vhdl
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-- Date: Mon Mar 4 17:58:35 2024
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-- Author: Yannick Reiß
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-- E-Mail: yannick.reiss@nickr.eu
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library work;
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library std;
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use std.textio.all;
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entity regs_tb is
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end regs_tb;
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architecture testing of regs_tb is
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signal clk : std_logic;
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constant clk_period : time := 10 ns;
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-- Inputs
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signal write_enable : std_logic;
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signal value_write : std_logic_vector(7 downto 0);
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signal register1 : std_logic_vector(2 downto 0);
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signal register2 : std_logic_vector(2 downto 0);
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signal value_r1 : std_logic_vector(7 downto 0);
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signal value_r2 : std_logic_vector(7 downto 0);
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begin
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uut : entity work.regs(Implementation)
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port map(
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clk => clk,
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write_enable => write_enable,
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value_write => value_write,
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register1 => register1,
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register2 => register2,
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value_r1 => value_r1,
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value_r2 => value_r2
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);
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clk_process : process -- runs always
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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end testing;
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