Wrong top module name in tet

2024-03-18 11:07:54 +01:00 · 2024-03-18 11:07:54 +01:00 · 814f78a122
parent fa728e5d53
commit 814f78a122
1 changed files with 1 additions and 1 deletions
--- a/test/tb.v
+++ b/test/tb.v
@ -23,7 +23,7 @@ module tb ();
  wire [7:0] uio_oe;

  // Replace tt_um_example with your module name:
-  tt_um_lights_out user_project (
+  tt_um_yannickreiss_lights_out user_project (

      // Include power ports for the Gate Level test:
 `ifdef GL_TEST