79 lines
2.5 KiB
Tcl
79 lines
2.5 KiB
Tcl
# DO NOT EDIT THIS FILE before reading the comments below:
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# This is the default configuration for Tiny Tapeout projects. It should fit most designs.
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# If you change it, please make sure you understand what you are doing. We are not responsible
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# if your project fails because of a bad configuration.
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# !!! DO NOT EDIT THIS FILE unless you know what you are doing !!!
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# If you get stuck with this config, please open an issue or get in touch via the discord.
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# Here are some of the variables you may want to change:
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# PL_TARGET_DENSITY - You can increase this if Global Placement fails with error GPL-0302.
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# Users have reported that values up to 0.8 worked well for them.
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set ::env(PL_TARGET_DENSITY) 0.6
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# CLOCK_PERIOD - Increase this in case you are getting setup time violations.
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# The value is in nanoseconds, so 20ns == 50MHz.
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set ::env(CLOCK_PERIOD) "20"
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# Hold slack margin - Increase them in case you are getting hold violations.
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set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.1
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set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.05
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# RUN_LINTER, LINTER_INCLUDE_PDK_MODELS - Disabling the linter is not recommended!
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set ::env(RUN_LINTER) 1
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set ::env(LINTER_INCLUDE_PDK_MODELS) 1
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# Configuration docs: https://openlane.readthedocs.io/en/latest/reference/configuration.html
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# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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# !!! DO NOT CHANGE ANYTHING BELOW THIS POINT !!!
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# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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# Load configuration auto-generated by tt-support-tools
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set script_dir [file dirname [file normalize [info script]]]
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source $::env(DESIGN_DIR)/user_config.tcl
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# Save some time
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set ::env(RUN_KLAYOUT_XOR) 0
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set ::env(RUN_KLAYOUT_DRC) 0
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# Don't put clock buffers on the outputs
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set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
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# Allow use of specific sky130 cells
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set ::env(SYNTH_READ_BLACKBOX_LIB) 1
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# Reduce wasted space
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set ::env(TOP_MARGIN_MULT) 1
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set ::env(BOTTOM_MARGIN_MULT) 1
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set ::env(LEFT_MARGIN_MULT) 6
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set ::env(RIGHT_MARGIN_MULT) 6
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# Absolute die size
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set ::env(FP_SIZING) absolute
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set ::env(PL_BASIC_PLACEMENT) {0}
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set ::env(GRT_ALLOW_CONGESTION) "1"
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set ::env(FP_IO_HLENGTH) 2
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set ::env(FP_IO_VLENGTH) 2
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# Use alternative efabless decap cells to solve LI density issue
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set ::env(DECAP_CELL) "\
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sky130_fd_sc_hd__decap_3 \
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sky130_fd_sc_hd__decap_4 \
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sky130_fd_sc_hd__decap_6 \
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sky130_fd_sc_hd__decap_8 \
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sky130_ef_sc_hd__decap_12"
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# Clock
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set ::env(RUN_CTS) 1
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set ::env(CLOCK_PORT) {clk}
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# Don't use power rings or met5 layer
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set ::env(DESIGN_IS_CORE) 0
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set ::env(RT_MAX_LAYER) {met4}
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