127 lines
3.2 KiB
Verilog
127 lines
3.2 KiB
Verilog
/*
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* Copyright (c) 2024 Yannick Reiß
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* SPDX-License-Identifier: Apache-2.0
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*/
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`define default_netname none
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module tt_um_yannickreiss_lights_out (
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input wire [7:0] ui_in, // Dedicated inputs
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output wire [7:0] uo_out, // Dedicated outputs
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input wire [7:0] uio_in, // IOs: Input path
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output wire [7:0] uio_out, // IOs: Output path
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output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
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input wire ena, // will go high when the design is enabled
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input wire clk, // clock
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input wire rst_n // reset_n - low to reset
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);
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// All output pins must be assigned. If not used, assign to 0.
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assign uio_oe = 8'b00000010;
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// Matrix (input)
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wire [8:0] buttons = {ui_in[7:0], uio_in[0]};
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// Matrix (current field)
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reg field1;
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reg field2;
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reg field3;
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reg field4;
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reg field5;
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reg field6;
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reg field7;
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reg field8;
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reg field9;
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// Matrix (output)
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assign uo_out[0] = field1;
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assign uo_out[1] = field2;
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assign uo_out[2] = field3;
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assign uo_out[3] = field4;
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assign uo_out[4] = field5;
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assign uo_out[5] = field6;
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assign uo_out[6] = field7;
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assign uo_out[7] = field8;
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assign uio_out[0] = field9;
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// uio_out map to zero
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assign uio_out[7:1] = 7'b0;
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always @(posedge clk) begin
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if (ena == 1'b1) begin
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if (rst_n == 1'b1) begin
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// Do act normal
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case (buttons)
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9'b000000001: begin
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field1 <= !field1;
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field2 <= !field2;
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field4 <= !field4;
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end
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9'b000000010: begin
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field1 <= !field1;
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field2 <= !field2;
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field3 <= !field3;
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field5 <= !field5;
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end
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9'b000000100: begin
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field2 <= !field2;
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field3 <= !field3;
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field6 <= !field6;
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end
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9'b000001000: begin
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field1 <= !field1;
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field4 <= !field4;
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field5 <= !field5;
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field7 <= !field7;
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end
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9'b000010000: begin
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field2 <= !field2;
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field4 <= !field4;
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field5 <= !field5;
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field6 <= !field6;
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field8 <= !field8;
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end
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9'b000100000: begin
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field3 <= !field3;
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field5 <= !field5;
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field6 <= !field6;
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field9 <= !field9;
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end
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9'b001000000: begin
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field4 <= !field4;
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field7 <= !field7;
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field8 <= !field8;
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end
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9'b010000000: begin
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field5 <= !field5;
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field7 <= !field7;
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field8 <= !field8;
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field9 <= !field9;
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end
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9'b100000000: begin
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field6 <= !field6;
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field8 <= !field8;
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field9 <= !field9;
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end
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default: begin
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end
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endcase
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end else begin
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// set new matrix in a pseudo random way
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field1 <= clk;
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field2 <= uio_in[7];
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field3 <= uio_in[6];
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field4 <= uio_in[5];
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field5 <= uio_in[4];
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field6 <= uio_in[3];
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field7 <= uio_in[2];
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field8 <= uio_in[1];
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field9 <= !clk;
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end
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end
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end
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endmodule
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