Test and project fix

2024-03-18 11:06:06 +01:00
parent 474f77b8b0
commit fa728e5d53
3 changed files with 3 additions and 5 deletions
--- a/test/Makefile
+++ b/test/Makefile
@@ -5,7 +5,7 @@
 SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 SRC_DIR = $(PWD)/../src
-PROJECT_SOURCES = project.v
+PROJECT_SOURCES = lights_out.v

 ifneq ($(GATES),yes)

@@ -32,7 +32,7 @@ VERILOG_SOURCES += $(PWD)/gate_level_netlist.v
 endif

 # Include the testbench sources:
-VERILOG_SOURCES += $(PWD)/tb.v 
+VERILOG_SOURCES += $(PWD)/tb.v
 TOPLEVEL = tb

 # MODULE is the basename of the Python test file