yannickreiss
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tt06_lights_out
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Test and project fix

This commit is contained in:
Yannick Reiß 2024-03-18 11:06:06 +01:00
parent 474f77b8b0
commit fa728e5d53
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GPG Key ID: 5A3AF456F0A0338C
3 changed files with 3 additions and 5 deletions
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2
src/lights_out.v
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@ -17,8 +17,6 @@ module tt_um_yannickreiss_lights_out (
); );
// All output pins must be assigned. If not used, assign to 0. // All output pins must be assigned. If not used, assign to 0.
assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
assign uio_out = 0;
assign uio_oe = 8'b00000010; assign uio_oe = 8'b00000010;
// Matrix (input) // Matrix (input)

4
test/Makefile
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@ -5,7 +5,7 @@
SIM ?= icarus SIM ?= icarus
TOPLEVEL_LANG ?= verilog TOPLEVEL_LANG ?= verilog
SRC_DIR = $(PWD)/../src SRC_DIR = $(PWD)/../src
PROJECT_SOURCES = project.v PROJECT_SOURCES = lights_out.v
ifneq ($(GATES),yes) ifneq ($(GATES),yes)
@ -32,7 +32,7 @@ VERILOG_SOURCES += $(PWD)/gate_level_netlist.v
endif endif
# Include the testbench sources: # Include the testbench sources:
VERILOG_SOURCES += $(PWD)/tb.v VERILOG_SOURCES += $(PWD)/tb.v
TOPLEVEL = tb TOPLEVEL = tb
# MODULE is the basename of the Python test file # MODULE is the basename of the Python test file

2
test/tb.v
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@ -23,7 +23,7 @@ module tb ();
wire [7:0] uio_oe; wire [7:0] uio_oe;
// Replace tt_um_example with your module name: // Replace tt_um_example with your module name:
tt_um_example user_project ( tt_um_lights_out user_project (
// Include power ports for the Gate Level test: // Include power ports for the Gate Level test:
`ifdef GL_TEST `ifdef GL_TEST