31 lines
686 B
Markdown
31 lines
686 B
Markdown
# Sample testbench for a Tiny Tapeout project
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This is a sample testbench for a Tiny Tapeout project. It uses [cocotb](https://docs.cocotb.org/en/stable/) to drive the DUT and check the outputs.
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## Setting up
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1. Edit [Makefile](Makefile) and modify `PROJECT_SOURCES` to point to your Verilog files.
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2. Edit [tb.v](tb.v) and replace `tt_um_example` with your module name.
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## How to run
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To run the RTL simulation:
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```sh
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make
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```
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To run gatelevel simulation, first harden your project and copy `../runs/wokwi/results/final/verilog/gl/{your_module_name}.v` to `gate_level_netlist.v`.
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Then run:
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```sh
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make GATES=yes
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```
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## How to view the VCD file
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```sh
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gtkwave tb.vcd tb.gtkw
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```
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